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Real-time clock (RTC)
RM0008
16.2
RTC main features
●
●
●
●
Programmable prescaler: division factor up to 2 20
32-bit programmable counter for long-term measurement
Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least
four times slower than the PCLK1 clock)
The RTC clock source could be any of the following three:
–
–
–
HSE clock divided by 128
LSE oscillator clock
LSI oscillator clock (refer to Section 6.2.8: RTC clock for details)
●
Two separate reset types:
–
–
The APB1 interface is reset by system reset
The RTC Core (Prescaler, Alarm, Counter and Divider) is reset only by a Backup
domain reset (see Section 6.1.3: Backup domain reset on page 75 ).
●
Three dedicated maskable interrupt lines:
–
–
–
Alarm interrupt, for generating a software programmable alarm interrupt.
Seconds interrupt, for generating a periodic interrupt signal with a programmable
period length (up to 1 second).
Overflow interrupt, to detect when the internal programmable counter rolls over to
zero.
16.3
16.3.1
388/995
RTC functional description
Overview
The RTC consists of two main units (see Figure 155 on page 389 ). The first one (APB1
Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit
registers accessible from the APB1 bus in read or write mode (for more information refer to
Section 16.4: RTC registers on page 392 ). The APB1 interface is clocked by the APB1 bus
clock in order to interface with the APB1 bus.
The other unit (RTC Core) consists of a chain of programmable counters made of two main
blocks. The first block is the RTC prescaler block, which generates the RTC time base
TR_CLK that can be programmed to have a period of up to 1 second. It includes a 20-bit
programmable divider (RTC Prescaler). Every TR_CLK period, the RTC generates an
interrupt (Second Interrupt) if it is enabled in the RTC_CR register. The second block is a
32-bit programmable counter that can be initialized to the current system time. The system
time is incremented at the TR_CLK rate and compared with a programmable date (stored in
the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR
control register.
Doc ID 13902 Rev 9
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